The present disclosure relates to a signal generation circuit and an electronic apparatus, and particularly to a signal generation circuit and an electronic apparatus that generate a clock signal in which jitter is reduced.
In the past, a clock generation circuit has been used to generate clock signals having various frequencies in an electronic apparatus. For example, a clock generation apparatus including a numerically controlled oscillator, a rounding module, a delay-locked loop (DLL), a multiplexer, and a flip-flop is proposed (see, for example, Japanese Patent Application Laid-open No. 2013-005050). The numerically controlled oscillator in the clock generation apparatus generates a clock signal NCOCLK based on a signal that represents a phase difference. The rounding module detects jitter in the clock signal NCOCLK.
Moreover, the DLL includes a phase comparator and a plurality of stages of delay elements. The phase comparator detects a phase difference between the signal supplied from the delay element in the final stage and a reference clock signal MCLK. Then, the plurality of stages of delay elements delay the reference clock signal MCLK by the delay time period depending on the detected phase difference, and generates a plurality of clock signals DCLK having different phases. Moreover, the multiplexer selects any one of the clock signals DCLK based on the jitter detected by the rounding module. The flip-flop holds the clock signal NCOCLK and outputs the held clock signal NCOCLK in synchronization with the selected clock signal DCLK (in other words, by retiming).
As described above, jitter is reduced because the flip-flop performs retiming on the clock signal NCOCLK based on the detected jitter.